On-Chip Communication Synthesis: Topology and Protocol Optimization

The main concern in modern chip design is definitely the communication structure that connect the components. Chip complexity is increasing constantly, making a chip look like a distributed set of communicating entities. In this paper a formal framework for the synthesis of an optimum onchip communication network is proposed. The major differences between network design and on chip network design are highlighted. This methodology starts from the communication constraints, in terms of connectivity and performance requirements, and defines an optimization problem whose solution is an optimum communication network that satisfies all the original constraints. The separation of topology design and protocol design is formalized and an example of the interaction between the two optimization problems is shown. The novelty of the algorithm resides in its formal definition and broad space of possible applications